I n Virtex-4 and Virtex-5 designs, determines if an operator, register, or module/architecture is placed in the DSP48 component.Ĭ ontrols the character formatting and style of bus signal names, port names, and vector ranges in the EDIF output file.Ĭ ontrols the character formatting of scalar signal and port names in the EDIF output file. I dentifies which signal to use as the enable input to an enable flip-flop when multiple candidates are possible.
#Synplify pro rom inference software#
The Synplify software does not support retiming.Ĭ hanges asynchronous reset registers, which cannot go into DSP48 blocks, into synchronous reset logic. S pecifies whether registers can be moved during retiming (applies to all Virtex technologies and the Spartan-II, Spartan-IIE, Spartan-IIE Automotive, Spartan-3, Spartan-3 Automotive, and Spartan-3E technologies).
Compile points are not supported in the Synplify tool. The value assigned to a given compile point includes the resources used by its children (at all levels). S pecifies allowed resources for compile points (applies to all Virtex, and Spartan-II, Spartan-IIE, Spartan-IIE Automotive, Spartan-3, Spartan-3 Automotive, and Spartan-3E technologies). S pecifies a parallel multiplexed structure in a Verilog case statement, rather than a priority-encoded structure. S pecifies a loop iteration limit for for loops.
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S pecifies that a Verilog case statement has covered all possible cases.
It is applied to a component, architecture, or module, with a value that specifies the set of pins on the module or entity. S pecifies that a pin on a black box is a tristate pin. S pecifies that a pin on a black box is an I/O pad.
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